Fpga Hardware Classifiers - Juniper JUNOSE SOFTWARE FOR E SERIES 11.3.X - POLICY MANAGEMENT CONFIGURATION GUIDE 2010-10-04 Configuration Manual

FPGA Hardware Classifiers

Copyright © 2010, Juniper Networks, Inc.
Table 18: Classifier Support (All Line Modules Except OC48/STM16, GE-2,
and GE-HDE)
Interface Type Hardware Classifier
All interface types –
Frame Relay Not supported
GRE tunnels Not supported
IP Destination address
Destination port
ICMP type and code
IGMP type
Protocol
Source address
Source port
IPv6 Destination address
Destination port
ICMPv6 type and code
Protocol
Source address
Source port
MPLS Not supported
VLAN Not supported
Classification is the process of taking a single data stream in and sorting it into multiple
output substreams. The classifier engine on an E Series router is a combination of PowerPC
processors, working with an FPGA for a hardware assist.
In the Differentiated Services (DiffServ) architecture, two basic types of classifiers exist.
The first classifier type is a multifield (MF) classifier. The MF classifier can examine
multiple fields in the IP datagram header to determine the service class to which a packet
belongs.
FPGA hardware classifiers are supported on all line modules except the OC48/STM16,
GE-2, and GE-HDE line modules. Table 18 on page 153 lists the FPGA classifiers and
software classifiers supported for each interface type.
An E Series router supports two versions of policies that are based on FPGA hardware
classifiers. One version has a maximum of 16 classifier entries per policy, and the second
version has 17 to 32 classifier entries per policy. The line module supports 16,255 policies
Chapter 8: Policy Resources
Software Classifier
Color
Traffic class
User packet class
DE bit
ToS
Destination route class
IP flags
IP fragmentation
Local
Source route class
TCP flags
ToS
Destination route class
Local
Source route class
TC field
TCP flags
EXP
User priority
153