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4.3.1 Chip select control function
Of the 256 MB memory area, the lower 8 MB (0000000H to 07FFFFFH) and the higher 8 MB (F800000H to
FFFFFFFH) can be divided into 2 MB memory blocks by chip area selection control registers 0 and 1 (CSC0, CSC1)
to control the chip select signal.
The memory area can be effectively used by dividing it into memory blocks using the chip select control function.
The priority order is described below.
(1) Chip area selection control registers 0, 1 (CSC0, CSC1)
These registers can be read/written in 16-bit units and become valid by setting each bit to 1.
If different chip select signal outputs are set to the same block, the priority order is controlled as follows.
CSC0: On-chip peripheral I/O area > CS0 > CS2 > CS1
CSC1: On-chip peripheral I/O area > CS7 > CS5 > CS6
If both the CS0m and CS2m bits of the CSC0 register are set to 0, CS1 is output to the corresponding block
(m = 0 to 3).
Similarly, if both the CS5m and CS7m bits of the CSC1 register are set to 0, CS6 is output to the
corresponding block (m = 0 to 3).
Caution Write to the CSC0 and CSC1 registers after reset, and then do not change the set values.
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CHAPTER 4 BUS CONTROL FUNCTION
User's Manual U14492EJ3V0UD
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