Chapter 3 Cpu Function; Features - NEC V850E/RS1 User Manual

The CPU of the V850E/RS1, which is based on RISC architecture, executes almost all instructions
in one clock cycle due to its five-stage pipeline control.

3.1 Features

• Number of instructions:
• Minimum instruction execution time:
• Memory space
• Program area:
• Data area:
• General-purpose registers:
• Internal 32-bit architecture
• 5-stage pipeline control
• Hardware interlock on register/flag hazards
• Instruction set
- Upwardly compatible with V850 CPU
- Multiplication/division instruction
- Saturated calculation instructions (with overflow/underflow detection function)
- 32-bit shift instructions: 1 clock
- Non blocking Load/store instruction with long/short format
- Multiplication can be performed in 1 or 2 clocks due to on-chip hardware multiplier:
- Four types of bit manipulation instructions:
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Chapter 3 CPU Function

- 16 bits × 16 bits → 32 bits
- 32 bits × 32 bits → 32 bits or 64 bits in one clock cycle.
- Set
- Clear
- Not
- Test
User's Manual U16702EE3V2UD00
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41.6 ns @ 24 MHz, 31.25 ns @ 32 MHz,
25 ns @ 40 MHz only for µPD70F3403 and µPD70F3403A
64 MB linear address space
4 GB linear address space
32 bits × 32 registers
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