Notes On Register Access - Hitachi SH7709S Hardware Manual

Bit 2: CKS2 Bit 1: CKS1
0 0
1
1 0
1
Note: If bits CKS2–CKS0 are modified when the WDT is running, the up-count may not be
performed correctly. Ensure that these bits are modified only when the WDT is not running.
9.7.3

Notes on Register Access

The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are
more difficult to write to than other registers. The procedure for writing to these registers is given
below.
Writing to WTCNT and WTCSR: These registers must be written to using a word transfer
instruction. They cannot be written to with a byte or longword transfer instruction. When writing
to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in
figure 9.3. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the
write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.
WTCNT write
Address: H'FFFFFE84
WTCSR write
Address: H'FFFFFE86
Bit 0: CKS0 Clock Division Ratio
0 1
1 1/4
0 1/16
1 1/32
0 1/64
1 1/256
0 1/1024
1 1/4096
15
H'5A
15
H'A5
Figure 9.3 Writing to WTCNT and WTCSR
Overflow Period
(when Pφ = 15 MHz)
17 µs
(Initial value)
68 µs
273 µs
546 µs
1.09 ms
4.36 ms
17.48 ms
69.91 ms
8 7
Write data
8 7
Write data
0
0
221