Status Change Diagram - Fujitsu MB90390 Series Hardware Manual

CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.6

Status Change Diagram

Figure 8.6-1 shows the status change diagram.
■ Status Change Diagram
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Figure 8.6-1 Status Change Diagram
Power-on
Power-on reset
Osc
Main clock mode
SLP=1
Main sleep mode
TMD=0
Main-
Time-base
timer mode
STP=1
Main stop
mode
Int
Main clock oscillation
stabilization wait
Int: Interrupt
Osc: Oscillation stabilization wait end
External reset, watchdog timer
reset, software reset
MCS=0
PLL clock mode
MCS=1
SLP=1
Int
PLL sleep mode
Int
TMD=0
PLL-
Time-base
timer mode
STP=1
PLL stop mode
Int
Osc
PLL clock oscillation
stabilization wait
Reset
Int
Int
Osc