Fujitsu MB90390 Series Hardware Manual page 143

■ Modulation Parameter Register Contents
Table 6.3-3 Function of Each Bit of the Modulation Parameter Register (CMPR)
Bit name
bit15,
Undefined
bit14
MP13 to MP0:
bit13 to
Modulation
bit0
Parameter bits
reference clock
modulated clock
F0:
T0:
resolution:
F :
min
F :
max
phase skew:
phase skew 50:
CMPR:
Depending on the PLL frequency the following modulation parameter settings are
possible. The corresponding CMPR register value is stated in the most right column.
n periods
n periods
n periods
Frequency of unmodulated input clock (PLL frequency)
Period of unmodulated input clock (PLL clock period)
resolution of frequencies in the modulated clock. "L" (1) to "H" (7)
minimal frequency occurring in the frequency modulated clock
maximal frequency occurring in the frequency modulated clock
The maximal phase shift of the modulated clock relative to the unmodulated
reference clock in terms of clock periods of the unmodulated clock.
Example: phase skew=1.44
In worst case, a sequence of n periods of the modulated clock can be 1.44 × T0
shorter or 1.44 × T0 longer than a sequence of n periods of the unmodulated
reference clock.
n can be any number > 50 periods
phase skew for sequences with n<= 50 periods
register setting of the CMPR register
CHAPTER 6 CLOCK MODULATOR
Function
-
+ -
phase skew
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