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CHAPTER 3 INTERRUPTS
3.5.2
Occurrence and Release of Hardware Interrupt
Figure 3.5-1 shows the occurrence and release of hardware interrupt.
■ Occurrence and Release of Hardware Interrupt
1. An interrupt cause occurs in a peripheral.
2. The interrupt enable bit in the peripheral is referenced. If interrupts are enabled, the peripheral issues an
interrupt request to the interrupt controller.
3. Upon reception of the interrupt request, the interrupt controller determines the priority levels of
simultaneously requested interrupts. Then, the interrupt controller transfers the interrupt level of the
corresponding interrupt to the CPU.
4. The CPU compares the interrupt level requested by the interrupt controller with the ILM bit of the
processor status register.
5. If the comparison shows that the requested level is higher than the current interrupt processing level, the
I flag value of the same processor status register is checked.
6. If the check in step 5. shows that the I flag indicates interrupt enable status, the requested level is
written to the ILM bit. Interrupt processing is performed as soon as the currently executing instruction
is completed, then control is transferred to the interrupt processing routine.
7. When the interrupt cause of step 1. is cleared by software in the user interrupt processing routine, the
interrupt request is completed.
The time required for the CPU to execute the interrupt processing in steps 6. and 7. is shown below.
Interrupt start:
Interrupt return: 15 + 6 × (Table 3.3-2 machine cycles) RETI instruction
66
Figure 3.5-1 Occurrence and Release of Hardware Interrupt
Register file
Microcode
IR
.
2
F
M C - 1 6 LX C P U
Peripheral
Enable FF
AND
Cause FF
24 + 6 × (Table 3.3-2 machine cycles)
PS
PS
I
ILM
I
ILM
IR
Comparator
Check
Interrupt
controller
:Processor status
:Interrupt enable flag
:Interrupt level mask register
:Instruction register
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