Fujitsu MB90390 Series Hardware Manual page 321

Table 18.4-3 Function Description of Each Bit of A/D Data Register 0 (ADCR0)
Bit name
S10:
A/D conversion
bit15
resolution selection
bit
ST1, ST0:
bit14
Sampling time
bit13
setting bit
CT1, CT0:
bit12
Comparison time
bit11
setting bit
-:
bit10
Undefined
D9 to D0:
bit9 to A/D conversion
bit0 end channel
selection bit
Notes:
• To rewrite the S10 bit, do so while the A/D is in a pause before conversion. If the bit is rewritten
after the conversion, the contents of ADCR0,ADCR1 become undefined.
• To read the contents of the ADCR0,ADCR1 register in 10-bit mode, use a word transfer
instruction (MOVW A, 002EH, etc.).
• This bit selects an A/D conversion resolution.
• Writing "0" to this bit selects a resolution of 10 bits, and writing "1" to this bit selects a
resolution of 8 bits.
Note:
The data bit to be used depends on the resolution.
• These bits select the sampling time for A/D conversion.
• When A/D conversion is activated, analog input is fetched during the time set in this
bit.
Note:
Setting these bits to "00
fetching of the analog voltage. The "00
• These bits select the comparison time for A/D conversion.
• After analog input is fetched (i.e., sampling time elapses), conversion result data is
defined and stored in bit9 to bit0 of this register after the time set in these bits.
Note:
Setting these bits to "00
acquisition of the analog conversion value. The "00
MHz.
• The A/D conversion results are stored and the register is rewritten each time conversion
ends.
• Usually, the last conversion value is stored.
• The initial value of this register is undefined.
Note:
The conversion data protection function is provided. (See Section "18.6 Operation of
the 8/10-Bit A/D Converter") Do not write data to these bits during A/D conversion.
CHAPTER 18 8/10-BIT A/D CONVERTER
Function
" during 16(20, 24)-MHz operation may disable normal
B
" setting is proposed for up to 8 MHz.
B
" during 16(20, 24)-MHz operation may disable normal
B
−
" setting is proposed for up to 8
B
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