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CHAPTER 20 UART2, UART3
Table 20.4-4 Function of Each Bit of the Extended Status/Control Register (ESCR2/ESCR3)
Bit name
LBIE:
LIN synch break
bit15
detection interrupt
enable bit
LBD:
bit14
LIN synch break
detected flag
LBL1/LBL0:
bit13
LIN synch break
bit12
length selection
SOPE:
Serial Output pin
bit11
direct access enable
SIOP:
Serial Input/Output
bit10
Pin direct access
CCO:
bit9
Continuos Clock
Output enable bit
SCES:
bit8
Sampling clock edge
selection bit
*: See Table 20.4-5.
360
This bit enables/disables LIN synch break interrupt.
LIN synch break interrupt is connected to the reception interrupt. When the LBD bit is
set and this bit is "1", a reception interrupt is signaled to the interrupt controller. This bit
is fixed to "0" in operation mode 1 and 2.
MB90V390H/MB90F394H(A): This bit goes to "1" if a LIN synch break was detected
in operating mode 0 or 3. When this bit goes to "1", the reception error flags (SSR2/
SSR3:FRE, SSR2/SSR3:ORE, SSR2/SSR3:PE) and the reception register full flag
(SSR2/SSR3:RDRF) are cleared.
MB90V390HA/MB90V390HB/MB90394HA: This bit goes to "1" if a LIN synch
break was detected in operating mode 3.
Writing a "0" to it clears this bit and the corresponding interrupt, if it is enabled.
It is recommended to write "0" to the RXE bit in the SCR2/SCR3 register before using
this bit.
Read-modify-write instructions always return 1. Note that this does not indicate a LIN
synch break.
These two bits determine how many serial bit times the LIN synch break is generated by
UART2, UART3. Receiving a LIN synch break is always fixed to 11 bit times.
Setting this bit to "1" enables the direct write to the SOT2/SOT3 pin, if SOE = 1 (SMR2/
*
SMR3).
*
Normal read instructions always return the actual value of the SIN2/SIN
to it sets the bit value to the SOT2/SOT3 pin, if SOPE = 1.
Notes:
• During a Read-Modify-Write instruction the bit returns the SOT2/SOT3 value in the
*
*
read cycle.
• A set value of this bit is effective only for the TXE bit of serial control register
(SCR) is "0".
This bit enables a continuos serial clock at the SCK2/SCK3 pin if UART2, UART3
operates in master mode 2 (synchronous) and the SCK2/SCK3 pin is configured as a
clock output.
Note:
When CCO bit is "1", use SSM bit of ECCR2/ECCR3 as setting to "1".
This bit inverts the serial clock signal in operation mode 2 (synchronous
communication). Receiving data is sampled at the falling edge of the internal clock. If
the MS bit of the ECCR2/ECCR3 register is "0" (master mode) and the SCKE bit of the
SMR2/SMR3 register is "1" (clock output enabled), the output clock signal is also
inverted.
MB90V390H/MB90F394H(A): During operation mode 0,1,3, this bit must be set to
"0".
MB90V390HA/MB90V390HB/MB90394HA: During operation mode 0,1,3, this bit is
fixed to "0".
Function
3
pin. Writing
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