Delayed Interrupt Register - Fujitsu MB90390 Series Hardware Manual

4.2

Delayed Interrupt Register

DIRR controls issuance and cancellation of delayed interrupt requests. Writing "1" to
this register issues a delayed interrupt request, and writing "0" cancels the delayed
interrupt request. Upon a reset, the request is canceled.
■ Delayed Interrupt Cause Issuance/Cancellation Register (DIRR: Delayed Interrupt
Request Register)
Address
00009F
R/W : Readable and writable
X : Undefined
- : Undefined bit
Table 4.2-1 Functional Explanation of Each Bit of the Delayed Interrupt Cause/Cancel Register (DIRR)
Bit name
-:
bit15 to bit9
Undefined bit
R0:
Delayed interrupt
bit8
request output bit
Figure 4.2-1 Delayed Interrupt Cause/Cancel Register (DIRR)
bit15 bit14 bit13
- - -
H
- - -
• When these bits are read, the values are undefined.
• Writing to these bits does not affect operation.
• This bit sets the generation/cancel of a delayed interrupt request.
• When this bit is "1", a delayed interrupt request is output.
• When this bit is "0", the delayed interrupt request is cleared.
• When a reset is specified, interrupt causes are canceled (cleared to "0").
CHAPTER 4 DELAYED INTERRUPT
bit12 bit11 bit10
- - -
- - -
Function
Initial value
bit9 bit8
XXXXXXX0
- R0
- R/W
B
83