Configuration Of The 8/10-Bit A/D Converter - Fujitsu MB90390 Series Hardware Manual

CHAPTER 18 8/10-BIT A/D CONVERTER
18.2

Configuration of the 8/10-Bit A/D Converter

The 8/10-bit A/D converter has nine blocks:
• A/D control status register (ADCS0, ADCS1)
• A/D data register (ADCR0, ADCR1)
• Clock selector (Input clock selector for activating A/D conversion)
• Decoder
• Analog channel selector
• Sample hold circuit
• D/A converter
• Comparator
• Control circuit
■ Block Diagram of the 8/10-bit A/D Converter
A/D control status register
(ADCS0/ADCS1)
16-bit reload timer 1 output
External trigger (ADTG)
PB6/AN14
PB5/AN13
PB4/AN12
PB3/AN11
PB2/AN10
PB1/AN9
PB0/AN8
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
ADSEL
A/D data register
(ADCR0/ADCS1)
φ
: Machine clock
- : Undefined
282
Figure 18.2-1 Block Diagram of the 8/10-bit A/D Converter
BUSY INT INTE PAUS STS1 STS0 STRT Reserved
Clock selector
Analog
channel
selector
S10 ST1 ST0 CT1 CT0
Interrupt request signal #31 (1F
MD1 MD0 ANS2
2
φ
Comparator
Sample
holding circuit
AVRH/AVRL
AVcc
D/A converter
AVss
D9 D8 D7 D6 D5
)
H
ANS1 ANS0 ANE2 ANE1 ANE0
6
Decoder
Control circuit
2
2
D4 D3 D2 D1 D0