Extended Communication Control Register (Eccr2/Eccr3) - Fujitsu MB90390 Series Hardware Manual

CHAPTER 20 UART2, UART3
20.4.6 Extended Communication Control Register (ECCR2/
ECCR3)
The extended communication control register provides bus idle recognition interrupt
settings, synchronous clock settings, and the LIN Synch break generation.

■ Extended Communication Control Register (ECCR2/ECCR3)

Figure 20.4-7 shows the bit configuration of the extended communication control registers (ECCR2/
ECCR3), and Table 20.4-6 shows the functions of each bit in the resisters.
Figure 20.4-7 Configuration of the Extended Communication Control Register (ECCR2/ECCR3)
bit
Address:
ECCR3: 00351C
H
ECCR2: 0035DC
H
362
7 6 5 4 3 2
- -
LBR MS SCDE SSM
-
-
W R/W R/W R/W
R/W : Readable and writable
R : Read only
W : Write only
X : Undefined value
- : Undefined
: Initial value
1 0
Initial value
X 0 0 0 0 X X X
B
RBI TBI
R R
bit0
TBI *
0 Transmission is ongoing
1 no transmission activity
bit1
RBI *
0 Reception is ongoing
1 no reception activity
bit2
Reading value is undefined. Always write "0".
bit3
SSM Synchronous start/stop bits in mode 2
0 No start/stop bits in synchronous mode 2
1 Enable start/stop bits in synchronous mode 2
bit4
SCDE Serial Clock Delay enable bit in mode 2
0 disable clock delay
1 enable clock delay
bit5
MS
0 Master mode (generating serial clock)
1 Slave mode (receiving external serial clock)
bit6
LBR
0 ignored
1
Generate LIN Synch break
bit7
Reading value is undefined. Always write "0".
* : Not used in mode2 when SSM = 0
T r ansmission bus idle
Reception bus idle
Unused bit
Master / Slave function in mode 2
Generating LIN synch break bit
write read
always read "0"
Unused bit