Fujitsu MB90390 Series Hardware Manual page 386

CHAPTER 20 UART2, UART3
■ Transmission Data Register (TDR2/TDR3)
When data to be transmitted is written to the transmission data register in transmission enable state, it is
transferred to the transmission shift register, then converted to serial data, and transmitted from the serial
data output terminal (SOT2/SOT3 pin). If the data length is 7 bits, the uppermost bit (D7) is not sent.
When transmission data is written to this register, the transmission data empty flag bit (SSR2/SSR3:
TDRE) is cleared to "0". When transfer to the transmission shift register is complete and starts, the bit is set
to "1". When the TDRE bit is "1", the next part of transmission data can be written. If output transmission
interrupt requests have been enabled, a transmission interrupt is generated. Write the next part of
transmission data when a transmission interrupt is generated or the TDRE bit is "1".
Note:
TDR2/TDR3 is a write-only register and RDR2/RDR3 is a read-only register. These registers are
located at the same address, so the read value is different from the write value. Therefore,
instructions that perform a read-modify-write (RMW) operation, such as the INC/DEC instruction,
cannot be used.
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