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CHAPTER 5 CLOCKS
■ Machine Clock
The machine clock may be a PLL clock output from the PLL multiplier circuit or a clock whose frequency
is the source oscillation frequency divided by 2. This machine clock is supplied to the CPU and peripheral
functions. The main clock or PLL clock can be selected by writing to the MCS bit of the clock selection
register (CKSCR).
■ Clock Modulator
For using the clock modulator, please refer to "CHAPTER 6 CLOCK MODULATOR".
Figure 5.4-1 shows the status change diagram for machine clock selection.
Figure 5.4-1 Status Change Diagram for Machine Clock Selection
Main
MCS = 1
MCM = 1
CS1, CS0 = XX
CS2 = x
(1)
(7)
Main
MCS = 0
MCM = 1
CS1, CS0 = XX
CS2 = x
PLL1
(7)
MCS = 1
MCM = 0
CS1, CS0 = 00
CS2 = 0
PLL2
(7)
MCS = 1
MCM = 0
CS1, CS0 = 01
CS2 = 0
PLL3
(7)
MCS = 1
MCM = 0
CS1, CS0 = 10
CS2 = 0
PLL4
(7)
MCS = 1
MCM = 0
CS1, CS0 = 11
CS2 = 0
98
(6)
(8)
(9)
(10)
PLLx
(11)
(2)
B
(3)
(4)
(5)
PLL1: Multiplied
Main
MCS = 0
MCM = 0
(6)
CS1, CS0 = 00
B
CS2 = 0
Main
PLL2: Multiplied
MCS = 0
MCM = 0
(6)
CS1, CS0 = 01
B
CS2 = 0
Main
PLL3: Multiplied
MCS = 0
MCM = 0
(6)
CS1, CS0 = 10
B
CS2 = 0
Main
PLL4: Multiplied
MCS = 0
MCM = 0
(6)
B
CS1, CS0 = 11
CS2 = 0
PLL2A
Main
(7)
MCS = 1
MCM = 0
B
CS1, CS0 = 00
CS2 = 1
PLL4A
Main
(7)
MCS = 1
MCM = 0
CS1, CS0 = 01
B
CS2 = 1
PLL6
Main
(7)
MCS = 1
MCM = 0
CS1, CS0 = 10
B
CS2 = 1
PLL8
Main
(7)
MCS = 1
MCM = 0
CS1, CS0 = 11
B
CS2 = 1
PLL2A:
Multiplied
MCS = 0
MCM = 0
(6)
CS1, CS0 = 00
B
B
CS2 = 1
PLL4A: Multiplied
MCS = 0
MCM = 0
(6)
CS1, CS0 = 01
B
B
CS2 = 1
PLL6: Multiplied
MCS = 0
MCM = 0
(6)
CS1, CS0 = 10
B
B
CS2 = 1
PLL8: Multiplied
MCS = 0
MCM = 0
(6)
B
CS1, CS0 = 11
B
CS2 = 1
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