Fujitsu MB90390 Series Hardware Manual page 379

Table 20.4-1 Functions of Each Bit of Control Register (SCR2/SCR3)
Bit name
PEN:
bit15
Parity enable bit
P:
bit14
Parity selection bit
SBL:
bit13 Stop bit length
selection bit
CL:
bit12 Data length selection
bit
A/D:
bit11 Address/Data
selection bit
CRE:
bit10 Clear reception error
flags bit
RXE:
bit9
Reception enable bit
TXE:
bit8 Transmission enable
bit
This bit selects whether to add a parity bit during transmission or detect it during
reception.
Parity is only provided in mode 0 and in mode 2 if SSM of the ECCR2/ECCR3 is
selected. This bit is fixed to "0" (no parity) in mode 1 and 3 (LIN).
When parity is provided and enabled this bit selects even (0) or odd (1) parity
This bit selects the length of the stop bit of an asynchronous data frame or a
synchronous frame if SSM of the ECCR2/ECCR3 is selected. This bit is fixed to "0" (1
stop bit) in mode 3 (LIN).
Note:
The bit length of the stop bit is detected whenever it is received.
This bit specifies the length of transmission or reception data. This bit is fixed to "1" (8
bits) in mode 2 and 3.
This bit specifies the data format in multiprocessor mode 1. Writing to this bit is
provided for a master CPU, reading from it for slave CPU. A "1" indicates an address
frame, a "0" indicates a usual data frame.
Note:
Please read the hints about using this bit in Section "20.8 Notes on Using UART2,
UART3".
This bit clears the FRE, ORE, and PE flag of the Serial Status Register (SSR2/SSR3).
Writing a "1" to it clears the error flag.
Writing a "0" has no effect.
Reading from it always returns "0".
Note:
Clear reception error flags after disabling the receive operation (RXE=0).
This bit enables/disables LIN-UART2, UART3 reception.
If this bit is set to "0", UART2, UART3 disables the reception of data frames.
If this bit is set to "1", UART2, UART3 enables the reception of data frames.
The LIN synch break detection in mode 3 remains unaffected.
Note:
If reception is disabled (RXE=0) during receiving, it is stopped immediately. In this
case, data is not guaranteed.
This bit enables/disables LIN-UART2, UART3 transmission.
If this bit is set to "0", UART2, UART3 disables the transmission of data frames.
If this bit is set to "1", UART2, UART3 enables the transmission of data frames.
Note:
If transmission is disabled (TXE=0) during transmitting, it is stopped immediately.
In this case, data is not guaranteed.
CHAPTER 20 UART2, UART3
Function
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