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CHAPTER 16 8/16-BIT PPG
Table 16.3-2 Bit Function Description of the PPG1 Operation Mode Control Register
Bit name
PEN1:
bit15
Operation enable bit
PE10:
bit13
PPG10 pin output
enable bit
PIE1:
bit12
PPG interrupt enable
bit
PUF1:
bit11
PPG counter
underflow bit
MD1, MD0:
bit10, bit9
PPG count mode
bit8
Reserved bit.
258
When set to "1", this bit enables the counter operation of the PPG. When operation
is disabled but output is enabled (bit13), a "L" level is maintained at the output.
When set to "1", this bit enables the pulse output. For MB90390 Series, the pulse
signal is output to the "PPG10" external pin. When disabled, the pin can be used as
general-purpose port.
While this bit is "1", an interrupt request is issued as soon as PUF1 is set to "1". No
interrupt request is issued while this bit is set to "0".
In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to
"1" when an underflow occurs as a result of the ch.0 counter value becoming from
"00
" to "FF
". In 16-bit PPG mode, this bit is set to "1" when an underflow occurs
H
H
as a result of the Channel 0 and 1 counter value changing from "0000
To set this bit to "0", write "0". Writing "1" to this bit has not effect. Upon a read
operation during a read-modify-write instruction, "1" is read.
These bits select the PPG timer operation mode as described in Figure 16.3-2. Do
not set "10
" in these bits.
B
To write "01
" to these bits, ensure that "01
B
PPGC0 or PEN1 bit of PPGC1. Write "11
bits simultaneously.
To write "11
" to these bits, update PPGC0 and PPGC1 by word transfer and write
B
"11
" or "00
" to both the PEN0 and PEN1 bits simultaneously.
B
B
This is a reserved bit. When setting PPGC1, always write "1" to this bit.
Function
" is not written to the PEN0 bit of
B
" or "00
" in both the PEN0 and PEN1
B
B
" to "FFFF
".
H
H
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