Fujitsu MB90390 Series Hardware Manual page 553

■ Pulse Width Control Register Contents
Table 24.2-1 Function of Each Bit of Pulse Width Control Register (PWCn)
Bit name
OE2:
bit7
Output enable 2 bit
OE1:
bit6
Output enable 1 bit
P1, P0:
bit5, bit4 Operation Clock
select bits
CE:
bit3
Count enable bit
bit2, bit1 Undefined
bit0 reserved bit
When this bit is set to "1", the external pins are assigned as PWM2Pn and PWM2Mn
outputs. Otherwise they can be used as general purpose I/O.
When this bit is set to "1", the external pins are assigned as PWM1Pn and PWM1Mn
outputs. Otherwise they can be used as general purpose I/O.
These bits specify the clock input signal for the PWM pulse generators.
P1 P0
0 0
0 1
1 0
1 1
This bit enables the operation of the PWM pulse generators. When it is set to "1", the
PWM pulse generators start their operation. Note that the PWM2 pulse generator starts
the operation one machine clock cycle after the PWM1 pulse generators is started. This
is to help reduce the switching noise from the output drivers.
This is a reserved bit. Always write "0" to this bit.
CHAPTER 24 STEPPING MOTOR CONTROLLER
Function
Clock Input
Machine clock
1/2 Machine clock
1/4 Machine clock
1/8 Machine clock
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