Fujitsu MB90390 Series Hardware Manual page 167

■ Clock Mode
●
PLL clock mode
In this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is used to operate the CPU and
peripheral functions.
●
Main clock mode
In this mode, the main clock, with the oscillation clock (HCLK) frequency divided by 2 is used to operate
the CPU and peripheral functions. In the main clock mode, the PLL multiplier circuit is inactive.
Reference:
For the clock mode, see Section "5.4 Clock Mode".
■ CPU Intermittent Operating Mode
In this mode, the CPU is operated intermittently while high-speed clock pluses are supplied to peripheral
functions, thereby reducing power consumption. In this mode, intermittent clock pulses are supplied only to
the CPU while it is accessing a register, internal memory, peripheral function, or external unit.
■ Standby Mode
In this mode, the low-power consumption control circuit stops supplying the clock to the CPU (sleep mode)
or the CPU and peripheral functions (time-base timer mode) or stops the oscillation clock itself (stop
mode), thereby reducing power consumption.
●
PLL sleep mode
The PLL sleep mode is activated to stop the CPU operating clock in the PLL clock mode. Components
excluding the CPU operate on the PLL clock.
●
Main sleep mode
The main sleep mode is activated to stop the CPU operating clock in the main clock mode. Components
excluding the CPU operate on the main clock.
●
Time-base timer mode
The time-base timer mode causes the operation of functions, excluding the oscillation clock, time-base
timer, and clock timer, to stop. All functions other than the time-base timer and clock timer are inactivated.
Please note that the status differentiates between Main-Time-base timer mode and PLL-Time-base timer
mode. The resulting state depends on the clock which is selected by the MCS-bit in CKSCR. See also
Figure 8.6-1.
The power consumption is significantly higher in PLL-Time-base timer mode. Please refer to your data
sheet for specific values.
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
139