Fujitsu MB90390 Series Hardware Manual page 471

■ Shift Clock Selection
The Shift Clock Mode Selection bits are used to select the serial shift clock mode, as shown in Table 22.2-
2. The second part is related to the Serial I/O prescaler register (CDCR). For details, see Section "22.3
Serial I/O Prescaler (CDCR)".
Table 22.2-2 Setting the Serial Shift Clock Mode
SMD2 SMD1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Table 22.2-3 Division Ratio for Serial I/O Prescaler Register
div
3
4
5
6
7
8
The SMD bits are initialized to "000
Shift operation can be performed for each instruction by specifying SCOE =0 during clock selection and by
using the ports that share the SCK4 pin.
φ=24MHz
SMD0
div=6
0 2 MHz
1 1 MHz
0 250 kHz
1 125 kHz
0 62.5 kHz
1
0 500 kHz
1 31.25 kHz
MD DIV3 DIV2
1 0
1 0
1 0
0 0
0 0
1 0
" upon a reset. These bits must not be updated during data transfer.
B
φ=20MHz φ=16MHz
div=4 div=4
2.5 MHz 2 MHz
1.25 MHz 1 MHz
312.5 kHz 250 kHz
156.25 kHz 125 kHz
78.125 kHz 62.5 kHz
External shift clock mode
625 kHz 500 kHz
39.1 kHz 31.25 kHz
DIV1 DIV0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
CHAPTER 22 SERIAL I/O
φ=8MHz φ=4MHz
div=4 div=4
1 MHz 500 kHz
500 kHz 250 kHz
125 kHz 62.5 kHz
62.5 kHz 31.25 kHz
31.25 kHz 15.625 kHz
250 kHz 125 kHz
15.625 kHz 7812.5 Hz
Recommended
machine cycle
6 MHz
8 MHz
10 MHz
12 MHz
14 MHz
16 MHz
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