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14.2.1
Timer Control Status Register (TMCSR)
Controls the operation mode and interrupts for the 16-bit timer. Only modify bits other
than UF, CNTE, and TRG when CNTE = 0.
■ Register Layout of Timer Control Register (TMCSR)
R/W
:
Readable and writable
X
:
Undefined value
-
:
Undefined
■ Register Contents of Timer Control Register (TMCSR)
[bit11, bit10] CSL1, CSL0 (Clock select 1, 0)
The count clock select bits. Table 14.2-1 lists the clock sources for CSL bit settings.
Table 14.2-1 Clock Sources for CSL Bit Settings
CSL1
0
0
1
1
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
Address:
bit
15
14
13
000051
H
-
-
-
000053
H
-
-
-
Address:
bit
7
6
5
000050
H
MOD0 OUTE OUTL RELD I NTE
000052
H
R/W
R/W R/W R/W R/W
CSL0
0
1
0
1
12
11
10
9
8
-
CSL1 CSL0 MOD2 MOD1
R/W R/W R/W R/W
-
4
3
2
1
0
UF
CNTE TRG
R/W R/W R/W
Clock Source (Machine cycle φ = 16 MHz)
External event count mode
TMCSR0/TMCSR1 (upper)
Initial value
X X X X 0 0 0 0
B
TMCSR0/TMCSR1 (lower)
Initial value
0 0 0 0 0 0 0 0
B
φ/2
1
(0.125 μs)
φ/2
(0.5 μs)
3
φ/2
(2.0 μs)
5
227
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