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Ten Bit Slave Address Register
Ten Bit Slave Address Register (ITBA) ............. 422
Ten Bit Slave Address Register (ITBA)
Contents............................................. 422
TIER
Transmission Interrupt Enable Register
(TIER) ............................................... 486
Time-base Counter
Time-base Counter........................................... 181
Time-base Timer
Block Diagram of Time-base Timer................... 178
Outline of Time-base Timer .............................. 178
Time-base Timer Control Register
Time-base Timer Control Register (TBTC) ........ 179
Time-base Timer Mode
Switching to the Time-base Timer Mode ............ 151
Watchdog Timer Behavior in Stop Mode, Time-base
Timer Mode, and Sleep Mode .............. 188
Timer Control Register
Register Contents of Timer Control Register
(TMCSR) ........................................... 227
Register Layout of Timer Control Register
(TMCSR) ........................................... 227
Timer Control Register (Lower) ........................ 240
Timer Control Register (Upper)......................... 242
Timing Limit Exceeded Flag
Timing Limit Exceeded Flag (DQ5)................... 570
TMCSR
Register Contents of Timer Control Register
(TMCSR) ........................................... 227
Register Layout of Timer Control Register
(TMCSR) ........................................... 227
TMD
Priorities of the STP,SLP,and TMD Bits ............ 146
TMR
Register Layout of 16-bit Timer Register (TMR)/
16-bit Reload Register (TMRLR) ......... 230
TMRLR
Register Layout of 16-bit Timer Register (TMR)/
16-bit Reload Register (TMRLR) ......... 230
Toggle Bit
Toggle Bit ....................................................... 686
Toggle Bit Flag
Toggle Bit Flag (DQ6) ..................................... 569
Toggle Bit-2 Flag
Toggle Bit-2 Flag (DQ2) .................................. 573
Tone Count Register
Tone Count Register......................................... 542
Transfer Data Format
Transfer Data Format ....................................... 327
Transition
Notes on the Transition to Standby Mode ........... 159
Transmission
Procedure for Transmission by Message
Buffer (x)............................................510
Transmission Cancel Register
Transmission Cancel Register (TCANR) ............484
Transmission Complete Register
Transmission Complete Register (TCR)..............485
Transmission Data Register
Transmission Data Register (TDR2/TDR3) .........358
Transmission Interrupt
Transmission Interrupt Generation and Flag Set
Timing................................................371
Transmission Interrupt Enable Register
Transmission Interrupt Enable Register
(TIER)................................................486
Transmission Request Register
Transmission Request Register (TREQR) ...........481
Transmission RTR Register
Transmission RTR Register (TRTRR) ................482
Transmit and Receive Operation
Status Flag during Transmit and Receive
Operation............................................333
Transmit Error Counters
Receive and Transmit Error Counters
(RTEC)...............................................476
Receive and Transmit Error Counters
(RTEC) Contents .................................476
Transmit Operation
Flag Set Timings for a Transmit Operation..........332
TREQR
Transmission Request Register (TREQR) ...........481
TRTRR
Transmission RTR Register (TRTRR) ................482
U
UART
Block Diagram of UART2, UART3 ...................342
Feature of UART0, UART1...............................312
Notes on using UART2, UART3........................401
Operation of UART2, UART3 ...........................380
UART0, UART1 Block Diagram .......................313
UART0, UART1 Operation Modes ....................322
UART0, UART1 Registers ................................314
UART2, UART3 as Master Device ....................399
UART2, UART3 Baud Rate Selection ................373
UART2, UART3 Direct Pin Access ...................392
UART2, UART3 Functions ...............................338
UART2, UART3 Pins .......................................347
UART2, UART3 Registers ................................349
UIDR
Input Data Register (UIDR) and Output Data Register
(UODR)..............................................319
UMC
Serial Mode Control Register (UMC) .................315
709
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