Fujitsu MB90390 Series Hardware Manual page 239

■ Sample Output Waveform with Two Compare Registers when CMOD[1:0] = 01
When CMOD[1:0] = 01
upon every match with the register value. This is identical to the behavior for CMOD[1:0] = 00
the output level of the second pin is reversed upon a match with either compare register 0 or compare
register 1 (3). This allows to define a pulsed signal with one edge defined by the value in compare register
0 and the other edge defined by compare register 1 (3) or vice versa. If both compare registers have the
same value, the operation is identical to the case for CMOD[1:0] = 00
A pulse width modulated signal with differing frequency can be defined by using this mode together with
the reset option by compare register match for the Free-run timer (MODE-bit in TCCSL0/TCCSL1
registers).
OUT0 (2): The level is only reversed by a match with compare register 0 (2).
OUT1 (3): The level is reversed by a match with compare register 0 (2) or with compare register 1 (3).
For OUT4, OUT5, OUT6 and OUT7, compare register 4 plays the same role as compare register 0 above.
Figure 13.4-7 Sample of a Output Waveform when CMOD[1:0] = 01
Counter value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Reset
OCCP0 value
OCCP1 value
OUT0
OUT1
Note: In this figure, the initial value is "0" for both pins.
Figure 13.4-8 Sample of a Output Waveform when CMOD[1:0] = 01
Counter value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Reset
OCCP0 value
OCCP1 value
OUT0
OUT1
Note: In this figure, the initial value is "0" for both pins.
, the output level of the pin corresponding to compare register 0 (2) is reversed
B
BFFF
H
7FFF
H
BFFF
H
7FFF
H
CHAPTER 13 16-BIT I/O TIMER
.
B
(No Timer Reset by Match)
B
Time
(With Timer Reset by Match)
B
Time
B
. However,
B
211