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8.5.2
Time-base Timer Mode
This mode causes all functions, excluding oscillation, the time-base timer, and the
clock timer, to stop. In this mode, only the time-base timer and clock timer operate.
■ Switching to the Time-base Timer Mode
When "0" is written to the TMD bit of the low-power consumption mode control register (LPMCR) in the
PLL clock mode or main clock mode, switching to the time-base timer mode occurs.
Please note that the status differentiates between Main-Time-base timer mode and PLL-Time-base timer
mode. The resulting state depends on the clock which is selected by the MCS-bit in CKSCR. See also
Figure 8.6-1.
The power consumption is significantly higher in PLL-Time-base timer mode. Please refer to your data
sheet for specific values.
●
Data retention function
In the time-base timer mode, the contents of dedicated registers, such as accumulators, and the built-in
RAM are retained.
●
Operation during an interrupt request
Writing "0" in the TMD bit of the low-power consumption mode control register (LPMCR) during an
interrupt request does not trigger a switch to the time-base timer mode.
●
Status of pins
Whether the external pins in the time-base timer mode retain the state they had immediately before
switching to the time-base timer mode or go to the high-impedance state can be controlled by the low-
power consumption mode control register (LPMCR: SPL).
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
151
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