Fujitsu MB90390 Series Hardware Manual page 124

CHAPTER 5 CLOCKS
Table 5.3-2 PLL and Special Configuration Control Register (PSCCR)
Bit name
bit15
Reserved:
to
Reserved bit
bit9
CS2:
bit8 Multiplier selection
bit2
Note:
The PSCCR register is a write-only register, so the read value is different from the write value. Therefore, instructions
that perform a read-modify-write (RMW) instructions, such as the INC/DEC instruction, cannot be used.
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• These bits are reserved bits.
• Always write "0" to these bits.
• Reading these bits always returns "X".
• This bit and CS1 and CS0 bits of the Clock selection register (CKSCR) select a PLL
clock multiplier.
• About the relationship between setting CS2, CS1 and CS0 bits and the PLL clock
multiplier selection, please see Table 5.3-1.
• This bit is initialized to "0" by all reset causes.
• Reading this bit always returns "X".
Note:
When the MCS or MCM bit is "0", changing the setting of this bit is not allowed.
Change this bit only after setting the MCS bit to "1" and waiting for MCM = 1 (main
clock mode).
Function