Fujitsu MB90390 Series Hardware Manual page 24

Reference: Main changes (Rev.2 → Rev.3)
Page
Figure 20.4-5 Transmission and Reception Data Registers (RDR2/RDR3 and TDR2/TDR3) is changed.
(RDR2/TDR2: 0035DA
357
("0 0 0 0 0 0 0 0
Summary of 20.4.5 Extended Status/Control Register (ESCR2/ESCR3) is changed.
359
Figure 20.4-6 Configuration of the Extended Status/Control Register (ESCR2/ESCR3) is changed.
(ESCR2: 0035DD
Table 20.4-4 Function of Each Bit of the Extended Status/Control Register (ESCR2/ESCR3)
Function of bit10 is changed.
("• A set value of this bit is effective only for the TXE bit of serial control register (SCR) is "0". " is added.)
360
Bit name of bit8 is changed.
(Serial clock edge selection bit → Sampling clock edge selection bit)
361 Table 20.4-5 Description of the Interaction of SOPE and SIOP is changed.
Figure 20.4-7 Configuration of the Extended Communication Control Register (ECCR2/ECCR3) is changed.
(ECCR2: 0035DC
362
(00000XXX
(BIE * is deleted in bit2)
Figure 20.4-8 Bit Configuration of Baud Rate Generator Register (BGR02/03 and BGR12/13)
BGR02: 0035DE
Access of bit15 is changed.
(- → R)
bit7 to bit0 is changed.
(BGR0 → BGR7 to BGR0)
364
(Baud rate Generator Register 0 → Baud rate Generator Register 02,03)
(Read bit 0 to 7 of actual count → Read bit 7 to 0 of transmission reload counter)
bit14 to bit8 is changed.
(BGR1 → BGR14 to BGR8)
(Baud rate Generator Register 1 → Baud rate Generator Register 12,13)
(Read bit 8 to 14 of actual count → Read bit 14 to 8 of transmission reload counter)
Table 20.5-1 Interrupt Control Bits and Interrupt Causes of LIN-UART2, UART3
365 Input Capture Unit is changed.
(ICP3, ICS23, ICE3 is added.)
● LIN Synchronization Field Edge Detection Interrupts is changed.
(ICU1/5 → ICU1/ICU3/ICU5)
367
Table 20.5-2 UART2, UART3 Interrupt and EI
● For UART2 Reception is changed.
368
● For UART2 Transmission is changed.
● Baud rates determined using the dedicated baud rate generator (reload counter) is changed.
(These baud rates are used in asynchronous mode or synchronous mode (master). To set the clock source,
select the internal clock and the use of the baud rate generator clock (SMR2/SMR3:EXT=0, OTO=0) is
added.)
373
● Baud rates determined using external clock (one-to-one mode) is changed.
(These baud rates are used in synchronous mode (slave). To set the clock source, select the external clock and
its direct use (SMR2/SMR3:EXT=1, OTO=1). is added.)
● Baud rates determined using the dedicated baud rate generator with external clock is changed.
■ Clearing Reload Counters is changed.
(Writing "0" to the REST bit does not clear the counters and they restart from reload value immediately. →
379
Writing "1" to the REST bit does not clear the counters and they restart from reload value immediately.)
Changes (For details, refer to main body.)
is changed.)
H
[TDR3] (MB90V390H/MB90F394H)" is deleted.)
B
is added.)
H
is added.)
H
→ X0000XXX
)
B B
and BGR12: 0035DF
H
are added.
H
2
OS is changed.
xx