Table of Contents
Advertisement
CHAPTER 15 WATCH TIMER
15.2.2
Sub-second Registers
The sub-second register stores a reload value for the 22-bit prescaler that divides the
oscillation clock. The reload value is usually set so that the 22-bit prescaler will output
exactly within a one-second cycle. This register is not initialized by reset, but 22-bit
prescaler is initialized by reset.
■ Sub-second Register
Sub-second register (0)
bit
Address:
00354A
H
00354B
H
Initial value:
Sub-second register (1)
Address:
00354C
H
R/W
:
Readable and writable
X
:
Undefined value
-
:
Undefined
Table 15.2-3 Sub-second Register
Bit name
bit15 to
WTBR (0):D15 to D0
bit0
bit5 to
WTBR (1):D21 to D16
bit0
244
Figure 15.2-4 Configuration of the Sub-second Register
15
14
13
12
11
10
D15
D14
D13
D12
D11
D10
R/W
R/W R/W
R/W
R/W
R/W
X
X
X
X
X
X
The Sub-second register stores the reload value for the 22-bit prescaler. This value
is reloaded after the reload counter reaches "0". Note that when modifying all
three bytes, make sure the reload operation will not be performed in between the
write instructions. Otherwise the 22-bit prescaler loads the incorrect value of the
combination of new data and old data bytes. It is generally recommended that the
Sub-Second register are updated while the ST bit is "0". If the sub-second registers
are set to "0", the 22-bit prescaler does not operate at all.
The input clock frequency always equals the oscillation clock frequency and it is
intended to be 4MHz or 5MHz. The reload value of the 22-bit prescaler for 4MHz
operation frequency is typically set to "1E847F
frequency: "26259F
9
8
7
6
5
4
D9
D8
D7
D6
D5
D4
R/W
R/W
R/W
R/W R/W
R/W
X
X
X
X
X
X
7
6
5
4
bit
-
-
D21
D20
-
-
R/W
R/W
Initial value:
X
X
X
X
Function
".
H
3
2
1
0
WTBR0
D3
D2
D1
D0
R/W
R/W
R/W
R/W
X
X
X
X
3
2
1
0
WTBR1
D19
D18
D17
D16
R/W
R/W
R/W
R/W
X
X
X
X
", and for 5MHz operation
H
Advertisement
Table of Contents
