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CHAPTER 12 WATCHDOG TIMER
■ Activation
The watchdog timer is activated by writing "0" to the WTE bit of the WDTC register while the watchdog
timer is stopped. At the same time, the WT1 and WT0 bits are used to set the watchdog timer reset interval.
Only the interval setting specified during activation is valid.
■ Watchdog Counter
Once the watchdog timer is activated, the watchdog timer counter must be periodically cleared within the
program. Writing "0" to the WTE bit of the WDTC register clears the watchdog counter. The watchdog
counter consists of a two-bit counter which uses the carry signals of the time-base timer as a clock source.
Therefore, the watchdog reset time may become longer than the setting if the time-base counter is cleared.
Figure 12.2-2 is a diagram of the watchdog timer operation.
Time-base
Watch-dog
WTE write
■ Watchdog Stop
The watchdog timer is stopped by transition to stop mode, time-base timer mode or sleep mode.
■ Watchdog Deactivation
The watchdog timer is deactivated by any kind of reset
■ Watchdog Timer Behavior in Stop Mode, Time-base Timer Mode, and Sleep Mode
When transition to stop mode, time-base timer, mode or sleep mode occurs, watchdog timer is cleared and
stops. When CPU is release from stop mode, time-base timer mode, or sleep mode, watchdog timer starts
counting again from cleared state (Table 12.2-1).
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Figure 12.2-2 Watchdog Timer Operation
00
01
Watchdog
Watchdog
activation
10
00
01
clear
10
11
00
Watchdog reset
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