Parity Bit - Fujitsu MB90390 Series Hardware Manual

CHAPTER 19 UART0, UART1
19.8

Parity Bit

The P bit in the URD0, URD1 register specifies whether to use even or odd parity when
parity is enabled. The PEN bit in the UMC0, UMC1 register enables parity.
■ Parity Bit
Inputting the data shown in Figure 19.8-1 to SIN when even parity is set causes a receive parity error.
Figure 19.8-1 also shows the data transmitted when sending "001101
SIN0
SOT0
SOT0
328
Figure 19.8-1 Serial Data with Parity Enabled
0 1 0 1 1
Start LSB
0 1 0 1 1
Start LSB
0 1 0 1 1
Start LSB
(Receive parity error occurs P = 0)
0 0 0 1
MSB Stop
(Parity)
(Even parity transmission P = 0)
0 0 1 1
MSB Stop
(Parity)
(Odd parity transmission P = 1)
0 0 0 1
MSB Stop
(Parity)
" with even parity and odd parity.
B