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23.6.16
Receive Overrun Register (ROVRR)
If RCx of the reception complete register (RCR) is "1" when completing storing of a
received message in the message buffer (x), ROVRx becomes "1", indicating that
reception has overrun.
■ Receive Overrun Register (ROVRR)
Figure 23.6-19 Configuration of the Receive Overrun Register (ROVRR)
Address:
CAN0: 00007D
CAN1: 00008D
CAN2: 00357D
CAN3: 00358D
CAN4: 00359D
Address:
CAN0: 00007C
CAN1: 00008C
CAN2: 00357C
CAN3: 00358C
CAN4: 00359C
[bit15 to bit0] ROVR15 to ROVR0:
Writing "0" to ROVRx results in ROVRx = 0. Writing "1" to ROVRx is ignored. After checking that
reception has overrun, write "0" to ROVRx to set it to "0".
"1" is read when a Read Modify Write (RMW) instruction is performed.
Note:
If setting to "1" by completion of the receive operation and clearing to "0" by writing occur at the
same time, the bit is set to "1".
bit
15
14
13
12
11
H
ROVR15 ROVR14 ROVR13 ROVR12 ROVR11 ROVR10 ROVR9 ROVR8
H
H
R/W R/W R/W R/W
R/W
H
H
7
6
5
4
3
bit
H
ROVR7 ROVR6 ROVR5 ROVR4 ROVR3 ROVR2 ROVR1 ROVR0
H
H
R/W R/W R/W R/W
R/W
H
H
CHAPTER 23 CAN CONTROLLER
10
9
8
ROVRRn (upper)
Initial value
0 0 0 0 0 0 0 0
R/W
R/W R/W
2
1
0
ROVRRn (lower)
Initial value
0 0 0 0 0 0 0 0
R/W
R/W R/W
B
B
n = 0, 1, 2, 3, 4
489
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