Fujitsu MB90390 Series Hardware Manual page 445

Table 21.2-2 Function of Each Bit of the Bus Control Register (IBCR) (3/3)
Bit name
INT:
bit8
Interrupt flag bit
This bit is the transfer end interrupt request flag. It is changed by the hardware and can
be cleared by the user. It always reads "1" in a Read-Modify-Write access.
Write access:
"0": Clear transfer end interrupt request flag
"1": No effect
Read access:
"0": Transfer not ended or not involved in current transfer or bus is idle
"1": Set at the end of a 1-byte data transfer or reception including the acknowledge bit
under the following conditions:
- Device is bus master.
- Device is addressed as slave.
- General call address received.
- Arbitration loss occurred.
Set at the end of an address data reception (after first byte if seven bit address received,
after second byte if ten bit address received) including the acknowledge bit if the device
is addressed as slave.
While this bit is "1" the SCL line will hold an "L" level signal. Writing "0" to this bit
clears the setting, releases the SCL line, and executes transfer of the next byte or a
repeated start or stop condition is generated. Additionally, this bit is cleared if a "1" is
written to the SCC bit or the MSS bit is being cleared.
CHAPTER 21 400 kHz I
Function
2
C INTERFACE
417