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Reference: Main changes (Rev.2 → Rev.3)
Page
● Reception operation is changed.
(To read received data, check the error flag status upon completion of reception of one-frame data and, if the
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data has been received normally, read the received data from the Reception Data Register (RDR2/RDR3). If a
reception error has occurred, perform error handling. is added.)
Figure 20.7-2 Data Transmitted with Parity Enabled is added.
● Data signaling method is added.
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● Data transfer method is added.
● Transfer data format is changed.
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● Clock supply is changed.
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● Communication is changed.
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(P: "0" for even parity, "1" odd parity → P: "1" for even parity, "0" odd parity)
Table 20.7-2 LIN Break Length is changed.
(LBL0 → LBL1)
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(LBL1 → LBL0)
● UART2, UART3 as LIN slave is changed.
(ICU counter register → ICU data register)
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(Note is added.)
Figure 20.7-9 LIN Bus Timing and UART2, UART3 Signals
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LBIE disable is changed.
■ UART2, UART3 Direct Pin Access is changed.
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Figure 20.7-10 Settings for UART2, UART3 Operation Mode 0 and 2
Mode0 of EXT is changed.
→ 0)
(
Mode0 of SCKE is changed.
→ 0)
(
Mode0 of LBIE is changed.
→ X)
(
Mode0 of LBD is changed.
→ X)
(
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Mode0 of LBL1 is changed.
→ X)
(
Mode0 of LBL0 is changed.
→ X)
(
Mode2 of CCO is changed.
→
(
)
Mode0 of SCES is changed.
(X → +)
Mode0 of LBR is changed.
→ 0)
(
Figure 20.7-13 Settings for UART2, UART3 Operation Mode 1
Mode1 of EXT is changed.
→ 0)
(
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Mode1 of SCKE is changed.
→ 0)
(
Mode1 of MD0 is changed.
(0 → 1)
Figure 20.7-15 Master/Slave Communication Flowchart is changed.
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(Set SOT3 pin as the serial data output pin. → Set SOT2/SOT3 pin as the port input pin.)
Changes (For details, refer to main body.)
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