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CHAPTER 6 CLOCK MODULATOR
Note:
Do not enable the modulator before the PLL lock time has elapsed. Do not disable the PLL while the
modulator is running.
■ Modulation Parameter for Frequency Modulation Mode
It is not possible to recommend a particular modulation parameter setting to achieve a particular reduction
in EMI. The best setting depends much on the actual application, the whole system and the requirements.
In order to find the optimal modulation parameter setting in frequency modulation mode, the following
approach is recommended.
1.
2.
3.
4.
5.
6.
122
define the required PLL frequency based on
performance needs
determine the maximal allowed clock frequency of
the MCU
choose the setting with the highest resolution and
the highest modulation degree, whose maximal
frequency is below the maximal allowed clock
frequency of the MCU.
perform EMI measurements
if the EMI measurements does not fulfill the
requirements, you may either
reduce the modulation degree at the same
frequency resolution
(this may improve the reduction in the upper
frequency band > 100 MHz, but decrease the
reduction of the fundamental < 100 MHz)
or
increase the modulation degree at a lower
frequency resolution
(this may improve the reduction of the fundamental
< 100 MHz, but worsen the reduction in the upper
frequency band > 100 MHz)
repeat item 3) with the new setting and continue
until the best settings is identified
e.g. 16 MHz
e.g. 32 MHz
e.g. resolution:7, degree:2, CMPR=05F2
(F
= 30.34 MHz)
max
e.g. resolution:7, degree:1, CMPR=03F9
or
e.g. resolution:5, degree:3, CMPR=0771
H
H
H
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