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Registers of Clock Modulator............................ 108
Clock Modulator Control Register
Clock Modulator Control Register (CMCR) ....... 109
Clock Output Enable Register
Clock Output Enable Register ........................... 103
Clock Selection Register
Clock Selection Registers ................................... 91
Configuration of the Clock Selection Register
(CKSCR) ............................................. 92
CMCR
Clock Modulator Control Register (CMCR) ....... 109
CMR
Common Register Bank Prefix (CMR)................. 48
Command Sequence
Chip Erase/Sector Erase Command
Sequence............................................ 685
Command Sequence Table
Command Sequence Table................................ 563
Common Register Bank Prefix
Common Register Bank Prefix (CMR)................. 48
Condition Code Register
Condition Code Register (CCR) .......................... 41
Conditions
Conditions for Canceling Bus Operation Stop
(HALT=0).......................................... 472
Configuration of the PLL and Special Configuration
Control Register
Configuration of the PLL and Special Configuration
Control Register (PSCCR) ..................... 95
Continuous Conversion Mode
Sample Program for Continuous Conversion Mode
2
OS....................................... 304
Using EI
Control Status Register
Control Status Register ..................................... 217
Control Status Register (CSR) (Lower) .............. 467
Control Status Register of Free-run Timer
(Lower).............................................. 198
Control Status Register of Output Compare
(Lower).............................................. 205
Control Status Register of Output Compare
(Upper) .............................................. 207
Count Clock
Selecting a Count Clock for 8/16-bit PPG........... 264
Counter Operation
Counter Operation State.................................... 235
Counting Example
Counting Example ........................................... 377
CPU
Outline of CPU Memory Space ........................... 27
Outline of the CPU............................................. 26
CPU Intermittent Operating Mode
CPU Intermittent Operating Mode ..................... 139
CPU Intermittent Operation Mode
CPU Intermittent Operation Mode ..................... 147
CPU Operating Modes
CPU Operating Modes and Current
Consumption.......................................138
CSR
Control Status Register (CSR) (Lower)...............467
Current Consumption
CPU Operating Modes and Current
Consumption.......................................138
D
Data Counter
Data Counter (DCT) ...........................................73
Data Direction Register
Data Direction Register .....................................174
Reading the Data Direction Register...................174
Data Frame
Processing for Reception of Data Frame and Remote
Frame .................................................505
Data Polling
Data Polling .....................................................686
Data Polling Flag
Data Polling Flag (DQ7) ...................................567
Data Read
Data Read by Read Access ................................682
Data Register
List of Message Buffers (DLC Registers and Data
Registers)............................................463
Data Register x
Data Register x (x=0 to 15) (DTRx) ...................499
DCT
Data Counter (DCT) ...........................................73
Decrement Grade Register
Decrement Grade Register.................................541
Delayed Interrupt
Block Diagram of Delayed Interrupt.....................82
Delayed Interrupt Cause Issuance/Cancellation
Register (DIRR: Delayed Interrupt Request
Register) ...............................................83
Delayed Interrupt Occurrence ..............................84
Delayed Interrupt Cause Issuance/Cancellation
Register
Delayed Interrupt Cause Issuance/Cancellation
Register (DIRR: Delayed Interrupt Request
Register) ...............................................83
Description
Description of Instruction Presentation Items and
Symbols..............................................643
Different Blocks
Explanation of the Different Blocks....................344
Direct Addressing
Direct Addressing .............................................625
Direct Pin Access
UART2, UART3 Direct Pin Access ...................392
699
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