Fujitsu MB90390 Series Hardware Manual page 712

APPENDIX
■ Write, Data Polling, Read (CE Control)
AQ18 to AQ0
WE
OE
CE
DQ7 to DQ0
5.0 V
PA: Write address
PD: Write data
DQ7: Reverse output of write data
D : Output of write data
OUT
Note:
The last two bus cycle sequences out of the four are described.
684
Figure C-3 Timing Diagram for Write access (CE Control)
Third bus cycle
7AAAA PA
H
t
WC
t
AS
t
WH
t
GHWL
t
CP
t
CPH
t
WS
t
DH
A0
H
t
DS
Data polling
t
AH
t
WHWH1
PD
DQ7
PA
D
OUT