Outline Of Dtp/External Interrupts - Fujitsu MB90390 Series Hardware Manual

CHAPTER 17 DTP/EXTERNAL INTERRUPTS
17.1

Outline of DTP/External Interrupts

The data transfer peripheral (DTP) is located between an external peripheral and the
2
F MC-16LX CPU. The DTP receives a DMA request or interrupt request from the external
peripheral, transfers the request to the F
service or interrupt processing.
■ Outline of DTP/External Interrupts
For the intelligent I/O service, "H" and "L" request levels are available. For an external interrupt request,
four request levels are available: "H", "L", rising edge, and falling edge.
For the MB90390 Series, the external bus interface is not supported. Therefore the DTP/External Interrupt
can not serve as the data transfer peripheral. It can be only used as the External Interrupt.
■ Block Diagram of DTP/External Interrupts
8
8
Gate
8
16
■ DTP/External Interrupts Registers
bit
Address : 000030
H
bit
Address : 000031
H
bit
Address : 000032
H
bit
Address : 000033
H
270
Figure 17.1-1 Block Diagram of DTP/external Interrupts
Interrupt/DTP enable register
Cause F/F
Interrupt/DTP cause register
Request level setting register
7 6 5 4
EN7 EN6 EN5 EN4
15 14 13 12
ER7 ER6 ER5 ER4
7 6 5 4
LB3 LA3 LB2 LA2
15 14 13 12
LB7 LA7 LB6 LA6
2
MC-16LX CPU to activate the intelligent I/O
Edge detection circuit
3 2 1 0
EN3 EN2 EN1 EN0
11 10 9 8
ER3 ER2 ER1 ER0
3 2 1 0
LB1 LA1 LB0 LA0
11 10 9 8
LB5 LA5 LB4 LA4
8
Request input
Interrupt/DTP enable register
(ENIR)
External interrupt request register
(EIRR)
Request level setting register
(ELVR)
Request level setting register
(ELVR)