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19.3.1
Serial Mode Control Register (UMC)
UMC specifies the operation mode of UART0, UART1. Set the operation mode while
operation is halted. However, the RFC bit can be accessed during operation.
■ Serial Mode Control Register (UMC)
Figure 19.3-1 Configuration of the Serial Mode Control Register (UMC)
bit
Address:
ch.0 000020
H
ch.1 000024
H
R/W R/W R/W R/W
R/W
W
7
6
5
4
3
2
R/W
W
R/W R/W
:
Readable and writable
:
Write only (read returns always "0")
:
Initial value
UMC0 UMC1
1
0
Initial value
0 0 0 0 0 1 0 0
bit0
SOE
0
disable SOT0,SOT1 pin (hi-Z)
1
enable SOT0,SOT1 pin (TxData)
bit1
SCKE
0
External Serial Clock Input
1
Internal Serial Clock Output
bit2
RFC
0
clear RDRF , ORFE, PE
1
no effect
bit3
SMDE
0
Start-Stop-CLK synchronous transfer
1
Asynchronous Transfer
bit5
bit4
MC1
MC0
0
0
0
1
1
0
1
1
bit6
SBL
0
1 bit
1
2 bit
bit7
PEN
0
Do not use parity
1
Use parity
CHAPTER 19 UART0, UART1
B
Serial Output enable
Serial Clock Output enable
Receiver Flag Clear
write
read
always "1"
Synchro mode enable
Operation Mode Setting
Mode 0: Asynchronous, 7(6) data bits
Mode 1: Asynchronous, 8(7) data bits
Mode 2: Async. Multiprocessor, 8+1 data bits
Mode 3: Asynchronous, (9)8 data bits
Stop bit length
Parity enable
315
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