Fujitsu MB90390 Series Hardware Manual page 394

CHAPTER 20 UART2, UART3
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Reception Interrupt
If one of the following events occurs in reception mode, the corresponding flag bit of the Serial Status
Register (SSR2/SSR3) is set to "1":
• Data reception is complete, i. e. the received data was transferred from the received shift register to the
Reception Data Register (RDR2/RDR3): (RDRF=1)
• Overrun error, i. e. RDRF = 1 and RDR2/RDR3 was not read by the CPU and next received data was
transferred to received data register (RDR2/RDR3) from received shift register: (ORE=1)
• Framing error, i. e. a stop bit was expected, but a "0"-bit was received: FRE
• Parity error, i. e. a wrong parity bit was detected: PE
If at least one of these flag bits above go "1" and the reception interrupt is enabled (SSR2/SSR3:RIE = 1), a
reception interrupt request is generated.
If the Reception Data Register (RDR2/RDR3) is read, the RDRF flag is automatically cleared to "0". Note
that this is the only way to reset the RDRF flag (for MB90V390H/MB90F394H(A), the RDRF flag is also
cleared when a LIN break is detected). The error flags are cleared to "0", if a "1" is written to the Clear
Reception Error (CRE) flag bit of the Serial Control Register (SCR2/SCR3). For MB90V390H/
MB90F394H(A), the error flags are also cleared when a LIN break is detected. The RDR2/3 contains only
valid data if the RDRF flag is "1" and no error bits are set.
Note, that the CRE flag is "write only" and by writing a "1" to it, it is internally held to "1" for one machine
clock cycle.
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Transmission Interrupt
If transmission data is transferred from the Transmission Data Register (TDR2/TDR3) to the transfer shift
register and transfer is started, the Transmission Data Register Empty flag bit (TDRE) of the Serial Status
Register (SSR2/SSR3) is set to "1". In this case an interrupt request is generated, if the Transmission
Interrupt Enable (TIE) bit of the SSR2/SSR3 was set to "1" before.
Note, that the initial value of TDRE (after hardware or software reset) is "1". So an interrupt is generated
immediately then, if the TIE flag is set to "1". Also note, that the only way to reset the TDRE flag is writing
data to the Transmission Data Register (TDR2/TDR3).
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LIN Synchronization Break Interrupt
MB90V390H/MB90F394H(A): This paragraph is only relevant, if UART2, UART3 operates in modes 0
If the bus (serial input) goes "0" (dominant) for more than 11 bit times, the LIN Break Detected (LBD) flag
bit of the Extended Status/Control Register (ESCR2/ESCR3) is set to "1", and the reception error flags
(SSR2/SSR3:FRE, SSR2/SSR3:ORE, SSR2/SSR3:PE) and the reception data register full flag (SSR2/
SSR3:RDRF) are cleared. Note, that in this case after 9 bit times the reception error flags are set to "1",
therefore the RXE flag has to be set to "0", if only a LIN synch break detect is desired.
The interrupt and the LBD flag are cleared after writing a "1" to the LBD flag. This has to be performed
before input capture interrupt for LIN synch field.
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or 3.