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Table 13.4-3 Function of CMOD1 and 0 Bits
Pin output value reversed upon match with register no.
OCS1
CMOD1
CMOD0
x
x
OCS3
CMOD1
CMOD0
0
0
1
1
OCS5
CMOD1
CMOD0
x
x
OCS7
CMOD1
CMOD0
0
0
1
1
Figure 13.4-5 Block Diagram of Output Selection (OCU Module 1)
Compare
Control 2
CMOD1
CMP0EXT
CMOD0
Compare
Control 3
For OCU module 1, which requires a match with Output Compare Register 0 if CMOD[1:0] = 10
comparison result from module 0 is carried inside by the CMP0EXT signal. Of course, this does not apply
to module 0 itself. Here, no other register can be used but OCCP0 and OCCP1.
The equivalent situation applies to OCU module 3, where the result from module 2 is needed as
CMP4EXT.
Register OCCPx
OUT0
0
0
1
0
Register OCCPx
OUT2
0
2
1
2
0
0/2
1
0/2
Register OCCPx
OUT4
0
4
1
4
Register OCCPx
OUT6
0
6
1
6
0
4/6
1
4/6
CHAPTER 13 16-BIT I/O TIMER
OUT1
1
0/1
OUT3
3
2/3
0/3
0/2/3
OUT5
5
4/5
OUT7
7
6/7
4/7
4/6/7
OUT2
OUT3
, the
B
209
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