Operation In Synchronous Mode (Operation Mode 2) - Fujitsu MB90390 Series Hardware Manual

20.7.2

Operation in Synchronous Mode (Operation Mode 2)

The clock synchronous transfer method is used for UART2, 3 operation mode 2 (normal
mode).
■ Operation in Synchronous Mode (Operation Mode 2)
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Transfer data format
In the synchronous mode, 8-bit data is transferred without start or stop bits if the SSM bit of the Extended
Communication Control Register (ECCR2/ECCR3) is "0". When the start/stop bits are used (ECCR2/
ECCR3:SSM=1), in addition, it can be selected to enable or disable the parity bit (SCR2/SCR3:PEN).
The figure below illustrates the data format during a transmission in the synchronous operation mode.
(ECCR2/ECCR3:SSM=0, SCR2/SCR3:PEN=0)
(ECCR2/ECCR3:SSM=1, SCR2/SCR3:PEN=0)
(ECCR2/ECCR3:SSM=1, SCR2/SCR3:PEN=1)
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Clock inversion and start/stop bits in mode 2
If the SCES bit of the Extended Status/Control Register (ESCR2/ESCR3) is set the serial clock is inverted.
Therefore in slave mode UART2, UART3 samples the data bits at the falling edge of the received serial
clock. Note, that in master mode if SCES is set the clock signal's mark level is "0". If the SSM bit of the
Extended Communication Control Register (ECCR2/ECCR3) is set the data format gets additional start and
stop bits like in asynchronous mode.
reception or transmission clock
(SCES = 0, CCO = 0):
reception or transmission clock
(SCES = 1, CCO = 0):
data stream (SSM = 1)
(here: no parity, 1 stop bit)
Figure 20.7-3 Transfer Data Format (Operation Mode 2)
Reception or transfer data
Reception or transfer data
Reception or transfer data
* only if SBL bit of SCR2/SCR3 is set to "1"
ST: Start bit SP: Stop bit
Figure 20.7-4 Transfer Data Format with Clock Inversion
D0 D1 D2 D3 D4 D5 D6
ST D0 D1 D2 D3 D4 D5
ST D0 D1 D2 D3 D4 D5
P : Parity bit
ST
data frame
CHAPTER 20 UART2, UART3
D7
*
D6 D7 SP SP
*
D6 D7 P SP SP
mark level
mark level
SP
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