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CHAPTER 12 WATCHDOG TIMER
12.1
Outline of Watchdog Timer
The watchdog timer consists of a two-bit watchdog counter, control register, and
watchdog reset controller. The two-bit watchdog counter uses the carry signals of an
18-bit time-base counter as a clock source.
■ Watchdog Timer Block Diagram
Figure 12.1-1 shows the diagram of the configuration of the watchdog timer.
Reset occurrence
Sleep mode
Time-base timer mode
Stop mode
Main clock
(HCLK divided by 2)
HCLK : Oscillation clock
184
Figure 12.1-1 Watchdog Timer Block Diagram
Watchdog timer control register (WDTC)
PONR
WRST ERST
Watchdog timer
Counter clear
Count clock
control circuit
(Time-base timer counter)
1
2
2
2
SRST
WTE
WT1 WT0
2
Activate
2-bit counter
selector
Clear
4
8
9
10
11
12
2
2
2
2
2
2
Deactivate
Watchdog reset
generation
circuit
13
14
16
17
2
2
15
2
2
2
Reset
occurrence
Internal reset
generation
circuit
18
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