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2.11
Precautions for Use of "DIV A, Ri" and "DIVW A, RWi"
Instructions
Set "00
" in the bank register before using the "DIV A, Ri" and "DIVW A, RWi"
H
instructions.
■ Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions
Table 2.11-1 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions (i = 0 to 7)
Bank register affected
by the execution of the
Instruction
instructions listed on the
DIV A, R0
DIV A, R1
DIV A, R4
DIV A, R5
DIVW A, RW0
DIVW A, RW1
DIVW A, RW4
DIVW A, RW5
DIV A, R2
DIV A, R6
DIVW A, RW2
DIVW A, RW6
DIV A, R3
DIV A, R7
DIVW A, RW3
DIVW A, RW7
*1: Depends on the S bit of the CCR register.
*2: In the event that the S bit of the CCR register is "0"
If the value of the bank registers (DTB, ADB, USB, and SSB) is "00
stored in the register of the instruction operands. Otherwise, the upper eight bits is specified by the bank
register corresponding to the register of the instruction operand, and the lower 16 bits is the same as the
address of the register of the instruction operand. The remainder is stored in the bank register specified by
the upper eight bits.
left
(DTB: Upper 8 bits) + (0180
(DTB: Upper 8 bits) + (0180
(DTB: Upper 8 bits) + (0180
(DTB: Upper 8 bits) + (0180
DTB
(DTB: Upper 8 bits) + (0180
(DTB: Upper 8 bits) + (0180
(DTB: Upper 8 bits) + (0180
(DTB: Upper 8 bits) + (0180
(ADB: Upper 8 bits) + (0180
(ADB: Upper 8 bits) + (0180
ADB
(ADB: Upper 8 bits) + (0180
(ADB: Upper 8 bits) + (0180
*2
(USB
: Upper 8 bits) + (0180
*2
(USB
: Upper 8 bits) + (0180
USB
*1
SSB
*2
(USB
: Upper 8 bits) + (0180
*2
(USB
: Upper 8 bits) + (0180
Address that stores the remainder
×
+ RP
10
+ 8
: Lower 16 bits)
H
H
H
×
+ RP
10
+ 9
: Lower 16 bits)
H
H
H
×
+ RP
10
+ C
: Lower 16 bits)
H
H
H
×
+ RP
10
+ D
: Lower 16 bits)
H
H
H
×
+ RP
10
+ 0
: Lower 16 bits)
H
H
H
×
+ RP
10
+ 2
: Lower 16 bits)
H
H
H
×
+ RP
10
+ 8
: Lower 16 bits)
H
H
H
×
+ RP
10
+ A
: Lower 16 bits)
H
H
H
×
+ RP
10
+ A
: Lower 16 bits)
H
H
H
×
+ RP
10
+ E
: Lower 16 bits)
H
H
H
×
+ RP
10
+ 4
: Lower 16 bits)
H
H
H
×
+ RP
10
+ E
: Lower 16 bits)
H
H
H
×
+ RP
10
+ B
H
H
H
×
+ RP
10
+ F
H
H
H
×
+ RP
10
+ 6
H
H
H
×
+ RP
10
+ E
H
H
H
", the remainder after division is
H
CHAPTER 2 CPU
: Lower 16 bits)
: Lower 16 bits)
: Lower 16 bits)
: Lower 16 bits)
51
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