Table of Contents
Advertisement
CHAPTER 21 400 kHz I
Table 21.2-1 Function of Each Bit of the Bus Status Register (IBSR) (2/2)
Bit name
GCA:
bit1
General call
address bit
ADT:
bit0
Address data
transfer bit
412
2
C INTERFACE
This bit indicates detection of a general call address (00
"0": General call address not received as slave.
"1": General call address received as slave.
This bit is cleared by a (repeated-) start or stop condition.
This bit indicates the detection of an address data transfer.
"0": Incoming data is not address data (or bus is not in use).
"1": Incoming data is address data.
This bit is set to "1" by a start condition. It is cleared after the second byte if a ten bit slave
address header with write access is detected, else it is cleared after the first byte.
"After" the first/second byte means:
- a "0" is written to the MSS bit during a master interrupt (MSS = 1 and INT = 1 in IBCR)
- a "1" is written to the SCC bit during a master interrupt (MSS = 1 and INT = 1 in IBCR)
- the INT bit is being cleared
- the beginning of every byte transfer if the interface is not involved in the current transfer
as master or slave
Function
).
H
Advertisement
Table of Contents
