Fujitsu MB90390 Series Hardware Manual page 435

■ Block Diagram of I
Figure 21.1-1 shows the block diagram of the I
2
C Interface
Figure 21.1-1 Block Diagram of I
ICCR
2
I C enable
EN
ICCR
Clock Divider 1
2 3 4 5 ... 32
CS4
CS3
5 5
Clock Selector
CS2
CS1
CS0 Clock Divider 2 (by 12)
SCL Duty Cycle Generator
IBSR
Bus busy
BB
Repeated star t
RSC
Last Bit
LRB
Send/receive
TRX
ADT
AL
Arbitration Loss Detector
IBCR
BER
BEIE
Interrupt Request
INTE
INT
IBCR
Start
SCC
Start-Stop Condition
Master
MSS
Generator
ACK enable
ACK
ACK Generator
GC-ACK enable
GCAA
8
IBSR
Slave
AAS
General call
GCA
ISMK
enable 7 bit mode
ENSB
ITMK
enable 10 bit mode
ENTB
received ad. length
RAL
10
ITBA
10
10
7
7
CHAPTER 21 400 kHz I
2
C interface.
2
C Interface
Synch
Bus Observer
Bus Error
Address Data
MCU
IRQ
IDAR
8
Slave Address
Comparator
7
10 7
ITMK ISBA ISMK
2
C INTERFACE
Shift Clock Generator
ICCR
NSF
enable
SCL
Noise
Filter
SDA
SCL
SDA
407