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Table 19.5-1 Baud Rate
24 MHz
BCH/
R
R
R
R
BCH0=
C
C
C
C
00
3
2
1
0
0
0
0
0
-
26/
0
0
0
1
38460
0
0
1
0
2/
0
0
1
1
500000
48/
0
1
0
0
20833
52/
0
1
0
1
19230
96/
0
1
1
0
10417
104/
0
1
1
1
9615
192/
1
0
0
0
5208
208/
1
0
0
1
4808
1
0
1
0
-
16/
1
0
1
1
62500
1
1
0
0
-
1
1
0
1
-
1
1
1
0
-
1
1
1
1
-
CLK asynchronous (μs/bps)
20 MHz
16 MHz
BCH/
BCH/
BCH0=
BCH0=
11
01
B
B
B
-
-
26/
26/
38460
38460
-
2/
2/
500000
500000
48/
48/
20833
20833
52/
52/
19230
19230
96/
96/
10417
10417
104/
104/
9615
9615
192/
192/
5208
5208
208/
208/
4808
4808
-
-
16/
16/
62500
62500
-
-
-
-
-
-
-
-
12 MHz
CLK
asynchronous
divider ratio
BCH/
BCH0=
10
B
×
-
8
12
26/
×
8
13
38460
-
8
2/
8
500000
48/
×
8
12
20833
52/
×
8
13
19230
96/
×
8
12
10417
104/
×
8
13
9615
192/
×
8
12
5208
208/
×
8
13
4808
-
8
16/
8
62500
-
-
-
-
-
-
-
-
CHAPTER 19 UART0, UART1
CLK synchronous (μs/bps)
24 MHz
20 MHz
16 MHz
BCH/
BCH/
BCH/
BCH0=
BCH0=
BCH0=
00
11
01
B
B
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5 / 2M
0.5 / 2M
0.5 / 2M
-
-
-
1 / 1M
1 / 1M
1 / 1M
-
-
-
2 / 500K
2 / 500K
2 / 500K
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12 MHz
BCH/
BCH0=
10
B
B
-
-
-
-
-
0.5 / 2M
-
1 / 1M
-
2 / 500K
-
-
-
-
-
-
325
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