Linear Bpi Flash Memory - Xilinx VC709 User Manual

VC709 Evaluation Board Features
Chapter 1:
Table 1-5: DDR3 SODIMM Socket J3 Connections to the FPGA (Cont'd)
XCVX690T (U1) Pin
AT20
AT16
AW16
AV16
AT19
BB19
AU16 DDR3_B_TEMP_EVENT_B
The VC709 DDR3 SODIMM interfaces adhere to the constraints guidelines documented in the
DDR3 Design Guidelines section of 7 Series FPGAs Memory Interface Solutions User Guide
(UG586)
Other memory interface details are also available in 7 Series FPGAs Memory Interface Solutions
User Guide (UG586)

Linear BPI Flash Memory

[Figure
The linear BPI flash memory located at U3 provides 128 MB of nonvolatile storage that can be used
for configuration or software storage. The data, address, and control signals are connected to the
FPGA. The BPI flash memory device is packaged in a 64-pin BGA.
•
•
•
•
The linear BPI flash memory can synchronously configure the FPGA in Master BPI mode at the
80 MHz data rate supported by the flash memory by using a configuration bitstream generated with
BitGen options for synchronous configuration. The fastest configuration method uses the external
80 MHz oscillator connected to the FPGA EMCCLK pin.
22
Send Feedback
Net Name
DDR3_B_CAS_B
DDR3_B_ODT0
DDR3_B_ODT1
DDR3_B_S0_B
DDR3_B_S1_B
DDR3_B_RESET_B
[Ref 4]. The VC709 DDR3 SODIMM interfaces are 40Ω impedance implementations.
[Ref 4] and 7 Series FPGAs Memory Resources User Guide (UG473)
1-2, callout 3]
Part number: PC28F00AG18FE/MT28GU01GAAA1EGC-0SIT
Note: MT28GU01GAAA1EGC-0SIT is a new Micron part, and either part might be installed
on the VC709 board.
Supply voltage: 1.8V
Datapath width: 16 bits (26 address lines and 7 control signals)
Data rate: Up to 80 MHz
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DDR3 SODIMM Memory J3
I/O Standard
Pin Number
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
Pin Name
115 CAS_B
116 ODT0
120 ODT1
114 S0_B
121 S1_B
30 RESET_B
198 EVENT_B
[Ref
VC709 Evaluation Board
UG887 (v1.6) March 11, 2019
5].