Linear Bpi Flash Memory - Xilinx VC709 User Manual

Table 1-5: DDR3 SODIMM Socket J3 Connections to the FPGA (Cont'd)
The VC709 DDR3 SODIMM interfaces adhere to the constraints guidelines documented in
the DDR3 Design Guidelines section of 7 Series FPGAs Memory Interface Solutions
User Guide (UG586). The VC709 DDR3 SODIMM interfaces are 40Ω impedance
implementations. Other memory interface details are available in
7 Series FPGAs Memory Resources User Guide (UG473).

Linear BPI Flash Memory

[Figure
The linear BPI flash memory located at U3 provides 128 MB of nonvolatile storage that can
be used for configuration or software storage. The data, address, and control signals are
connected to the FPGA. The BPI flash memory device is packaged in a 64-pin BGA.
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The linear BPI flash memory can synchronously configure the FPGA in Master BPI mode at
the 40 MHz data rate supported by the PC28F00AG18FE flash memory by using a
configuration bitstream generated with BitGen options for synchronous configuration and
for configuration clock division. The fastest configuration method uses the external
80 MHz oscillator connected to the FPGA's EMCCLK pin with a bitstream that has been
built to divide the configuration clock by two. The division is necessary to remain within
the synchronous read timing specifications of the flash memory.
Multiple bitstreams can be stored in the linear BPI flash. The two most significant address
bits (A25, A24) of the flash memory are connected to DIP switch SW11 positions 1 and 2
respectively, and to the RS1 and RS0 pins of the FPGA. By placing valid XC7VX690T
bitstreams at four different offset addresses in the flash memory, 1 of the 4 bitstreams can
VC709 Evaluation Board
UG887 (v1.0) February 4, 2013
XCVX690T (U1) Pin
AU18
AW17
AW18
AV19
AU19
AT20
AT16
AW16
AV16
AT19
BB19
AU16 DDR3_B_TEMP_EVENT_B
1-2, callout 3]
Part number: PC28F00AG18FE (Numonyx)
Supply voltage: 1.8V
Datapath width: 16 bits (26 address lines and 7 control signals)
Data rate: Up to 40 MHz
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Net Name
DDR3_B_CLK1_P
DDR3_B_CKE0
DDR3_B_CKE1
DDR3_B_RAS_B
DDR3_B_WE_B
DDR3_B_CAS_B
DDR3_B_ODT0
DDR3_B_ODT1
DDR3_B_S0_B
DDR3_B_S1_B
DDR3_B_RESET_B
Feature Descriptions
SODIMM Memory J3
Pin Number Pin Name
104 CK1_N
73 CKE0
74 CKE1
110 RAS_B
113 WE_B
115 CAS_B
116 ODT0
120 ODT1
114 S0_B
121 S1_B
30 RESET_B
198 EVENT_B
UG586 and
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