Linear Bpi Flash Memory - Xilinx KC705 User Manual

Chapter 1: KC705 Evaluation Board Features
Table 1-4: DDR3 Memory Connections to the FPGA (Cont'd)
The KC705 DDR3 SODIMM interface adheres to the constraints guidelines documented in
the DDR3 Design Guidelines section of UG586, 7 Series FPGAs Memory Interface Solutions
User Guide. The KC705 DDR3 SODIMM interface is a 40Ω impedance implementation.
Other memory interface details are available in
Resources User Guide. For more information about the Micron MT8JTF12864HZ-1G6G1 see
[Ref

Linear BPI Flash Memory

[Figure
The Linear BPI Flash memory located at U58 provides 128 MB of nonvolatile storage that
can be used for configuration or software storage. The data, address, and control signals
are connected to the FPGA. The BPI Flash memory device is packaged in a 64-pin BGA.
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The Linear BPI Flash memory can synchronously configure the FPGA in Master BPI mode
at the 33 MHz data rate supported by the PC28F00AP30TF Flash memory by using a
configuration bitstream generated with bitgen options for synchronous configuration and
for configuration clock division. The fastest configuration method uses the external
66 MHz oscillator connected to the FPGA EMCCLK pin with a bitstream that has been
built to divide the configuration clock by two. The division is necessary to remain within
the synchronous read timing specifications of the Flash memory.
Multiple bitstreams can be stored in the Linear BPI Flash. The two most significant address
bits (A25, A24) of the Flash memory are connected to DIP switch SW13 positions 1 and 2
respectively, and to the RS1 and RS0 pins of the FPGA. By placing valid XC7K325T
bitstreams at four different offset addresses in the Flash memory, 1 of the 4 bitstreams can
be selected to configure the FPGA by appropriately setting the DIP switch SW13. The
connections between the BPI Flash memory and the FPGA are listed in
16
U1 FPGA Pin Net Name
AF10 DDR3_CKE0
AE10 DDR3_CKE1
AH10 DDR3_CLK0_N
AG10 DDR3_CLK0_P
AF11 DDR3_CLK1_N
AE11 DDR3_CLK1_P
5].
1-2, callout 3]
Part number: PC28F00AP30TF (Numonyx)
Supply voltage: 2.5V
Datapath width: 16 bits (26 address lines and 7 control signals)
Data rate: Up to 33 MHz
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J1 DDR3 Memory
Pin Number Pin Name
73 CKE0
74 CKE1
103 CK0_N
101 CK0_P
104 CK1_N
102 CK1_P
UG586 and UG473, 7 Series FPGAs Memory
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013
Table 1-5.