Linear Bpi Flash Memory - Xilinx VCU118 User Manual

Linear BPI Flash Memory

[Figure 2-1, callout 6]
The linear BPI flash memory located at U133 provides 128 MB (1 Gbit) of nonvolatile
storage that can be used for configuration or software storage. The data, address, and
control signals are connected to the U1 XCVU9P bank 65. The BPI flash memory device is
packaged in a 64-pin BGA.
• Part number: MT28GU01GAAA1EGC-0SIT (Micron)
• Supply voltage: 1.8V
• Datapath width: 16 bits (with 26 address lines and 7 control signals)
• Data rate: up to 90 MHz
The linear BPI flash memory can synchronously configure the FPGA in master BPI mode at
the 90 MHz data rate supported by the MT28GU01GAAA1EGC flash memory by using a
configuration bitstream generated with BitGen options for synchronous configuration and
for a configuration clock division of one. The fastest configuration method uses the
external 90 MHz oscillator connected to the FPGA bank 65 EMCCLK pin AL20. By default,
UltraScale FPGAs use the parallel NOR flash asynchronous read in the master BPI
configuration mode.
A full XCVU9P 641,272,864-bit uncompressed bitstream requires 60% of the 1 Gbit linear
BPI NOR flash size, so one XCVU9P bitstream is supported.
The BPI flash upper address A25 pin is wired to pull-up header J29 to allow one of two
compressed bitstreams to be manually selected.
See the UltraScale Architecture Configuration User Guide (UG570)
information.
Add these constraints for compression to designs targeted for the VCU118 board.
• When loading from BPI flash:
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design]
set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design]
set_property CONFIG_MODE BPI16 [current_design]
*set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
Compression is an optional setting that can improve indirect flash programming time.
Note:
• To match the VCU118 configuration of FPGA U1 bank 0:
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Chapter 3: Board Component Descriptions
www.xilinx.com
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