Linear Bpi Flash Memory - Xilinx VC707 User Manual

Table 1-4: DDR3 Memory Connections to the FPGA (Cont'd)
The VC707 DDR3 SODIMM interface adheres to the constraints guidelines in the DDR3
Design Guidelines section of UG586, 7 Series FPGAs Memory Interface Solutions User Guide.
The VC707 DDR3 SODIMM interface is a 40Ω impedance implementation. Other memory
interface details are available in UG586 and UG473, 7 Series FPGAs Memory Resources
User Guide.

Linear BPI Flash Memory

[Figure
The Linear BPI Flash memory located at U3 provides 128 MB of nonvolatile storage that
can be used for configuration or software storage. The data, address, and control signals
are connected to the FPGA. The BPI Flash memory device is packaged in a 64-pin BGA.
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The Linear BPI Flash memory can synchronously configure the FPGA in Master BPI mode
at the 40 MHz data rate supported by the PC28F00AG18FE flash memory by using a
configuration bitstream generated with bitgen options for synchronous configuration and
for configuration clock division. The fastest configuration method uses the external
VC707 Evaluation Board
UG885 (v1.2) February 1, 2013
FPGA (U1)
Net Name
Pin
E28 DDR3_DQS7_N
E27 DDR3_DQS7_P
H20 DDR3_ODT0
H18 DDR3_ODT1
C29 DDR3_RESET_B
J17 DDR3_S0_B
J20 DDR3_S1_B
G17 DDR3_TEMP_EVENT
F20 DDR3_WE_B
K17 DDR3_CAS_B
E20 DDR3_RAS_B
K19 DDR3_CKE0
J18 DDR3_CKE1
G18 DDR3_CLK0_N
H19 DDR3_CLK0_P
F19 DDR3_CLK1_N
G19 DDR3_CLK1_P
1-2, callout 3]
Part number: PC28F00AG18FE (Numonyx)
Supply voltage: 1.8V
Datapath width: 16 bits (26 address lines and 7 control signals)
Data rate: Up to 40 MHz
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Feature Descriptions
J1 DDR3 Memory
Pin Number Pin Name
186 DQS7_N
188 DQS7_P
116 ODT0
120 ODT1
30 RESET_B
114 S0_B
121 S1_B
198 EVENT_B
113 WE_B
115 CAS_B
110 RAS_B
73 CKE0
74 CKE1
103 CK0_N
101 CK0_P
104 CK1_N
102 CK1_P
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