Ddr3 Memory - Xilinx VC707 User Manual

Table 1-3: I/O Voltage Rails (Cont'd)
Notes:
1. The VADJ_FPGA rail can support up to 1.8V due to FPGA HP

DDR3 Memory

[Figure
The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module
(SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM)
for storing user code and data.
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The DDR3 interface is implemented across I/O banks 37, 38, and 39. Each bank is a 1.5V
high-performance bank having a dedicated DCI VRP/N resistor connection. An external
0.75V reference VTTREF is provided for data interface banks 37 and 39. Any interface
connected to these banks that requires a reference voltage must use this FPGA voltage
reference. The connections between the DDR3 memory and the FPGA are listed in
Table
Table 1-4: DDR3 Memory Connections to the FPGA
VC707 Evaluation Board
UG885 (v1.2) February 1, 2013
FPGA (U1) Power Supply Rail
Bank Net Name
Bank 35 VADJ_FPGA
Bank 36 FMC1_VIO_B_M2C
Bank 37 VCC1V5_FPGA
Bank 38 VCC1V5_FPGA
Bank 39 VCC1V5_FPGA
bank connections to FMC. For more information on
VADJ_FPGA see Power Management, page
1-2, callout 2]
Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)
Supply voltage: 1.5V
Datapath width: 64 bits
Data rate: Up to 1,600 MT/s
1-4.
FPGA (U1)
Net Name
Pin
A20 DDR3_A0
B19 DDR3_A1
C20 DDR3_A2
A19 DDR3_A3
A17 DDR3_A4
A16 DDR3_A5
D20 DDR3_A6
C18 DDR3_A7
D17 DDR3_A8
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Voltage
1.8V (default)
Variable
1.5V
1.5V
1.5V
65.
J1 DDR3 Memory
Pin Number Pin Name
98
97
96
95
92
91
90
86
89
Feature Descriptions
A0
A1
A2
A3
A4
A5
A6
A7
A8
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